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www.semtech.com 1 power management portable, vid programmed single phase power supply controller SC453 high speed hysteretic controller single phase operation selectable analog or vid controlled sleep setting 6 bit vid programmable output integrated drivers with soft-high side turn-on programmable soft-start programmable boot voltage programmable sleep voltage with sleep mode under-voltage lockout on vcca over-voltage protection on core current limit protection on core thermal protection power good flag with blanking during v core changes automatic power save at light load tssop-28 package august 25, 2006 description features the SC453 ic is a single chip high-performance hysteretic pwm controller. with its integrated smartdriver?, it pow- ers advanced graphics and core processors. it provides sleep mode and boot voltage support. automatic "power- save" is present to prevent negative current flow in the low-side fet during light loading conditions saving even more power. the high side driver initially turns on with a weak drive to reduce ringing, emi, and capacitive turn-on of the low side. a 6-bit dac, accurate to 0.85%, sets the output voltage reference, and implements the 0.700v to 1.708v range required by the processor. the hysteretic converter uses a comparator without an error amplifier, and therefore pro- vides the fastest possible transient response, while avoid- ing the stability issues inherent to classical pwm control- lers. the dac is externally slew rate limited to minimize transient currents and audible noise. the SC453 operates from 5vdc and also features soft- start, an open-drain pwrgd signal with power good blank- ing, and an enable input. programmable current limiting shuts down the SC453 after 32 current limit pulses. low power notebook and laptop computers embedded applications typical application circuit applications features powerstep iv? and smart driver? are trademarks of semtech corporation. SC453 single phase power supply smart driver pwm controller vid logic and dac vid (5:0) vin v 5 v cca vcore 0.700v-1.708v
2 ? 2006 semtech corp. www.semtech.com power management SC453 1 2 r1 10 1 2 r12 332 1 2 c7 10uf 1 2 c12 330pf 1 2 c4 10uf 1 2 r2 0 1 2 r10 dnp 1 2 3 4 5 6 l1 0.5uh 4 1 2 3 5 6 7 8 d q1 irf7821 1 2 c6 1uf 1 2 c14 4.7uf 1 2 c9 1uf 1 2 + c15 330uf 1 2 c2 10uf 1 2 c13 1nf 4 1 2 3 5 6 7 8 d q2 irf7821 1 2 + c18 330uf hys 1 2 r4 33.2k 1 2 r8 1.8k +v core vid4 pg_ del vid0 vid5 pg# +vcore vid3 vid1 slp en vid2 bg vid3 vid4 vid5 vid2 vcca cl 1 2 r13 dnp dac bootv +5v pg_del drn +v_in slp tg pg# bst bst_l drn 1 tg 2 bst 3 slp 4 slpv 5 bootv 6 pg# 7 hys 8 vid5 9 vid4 10 vid3 11 vid2 12 vid1 13 vid0 14 ss 15 pg_del 16 core 17 dac 18 gnd 19 refin 20 vcca 21 clrf 22 cmp 23 cl 24 en 25 pgnd 26 bg 27 v5 28 u1 SC453 ss core cmp vid1 slpv en vid0 csh csh csh csh clrf 1 2 r3 54.9k 1 2 r7 931 1 2 c10 1nf 1 2 d2 mbr s140l 1 2 c22 330pf 1 2 c5 10uf 1 2 r9 0.001 4 1 2 3 5 6 7 8 d q4 irf7832 1 2 c23 1nf 1 2 c21 15nf 4 1 2 3 5 6 7 8 d q3 irf7832 1 2 r5 36.5k 1 2 r11 0 1 2 c3 10uf 1 2 + c16 330uf 1 2 + c17 330uf 1 2 r6 1.8k 1 2 d1 mbr0530 1 2 c1 1uf 1 2 c11 270pf 1 2 c8 10uf reference design
3 ? 2006 semtech corp. www.semtech.com power management SC453 absolute maximum ratings exceeding the speci cations below may result in permanent damage to the device or device malfunction. operation outside of the parameters speci ed in the electrical characteristics section is not implied. unless otherwise speci ed: v in = 15v, v cca = 5v, and v5 = 5v. notes: (1) calculated from package in still air, mounted to 3? x 4.5?, 4 layer fr4 pcb. (2) tested according to jedec standard jesd22-a114-b. parameter symbol conditions min max units supply voltages v cca, v 5 -0.3 7 v input and output voltages vslpv, v slp, v vid [0.5], v dac, v refin, v cmp, v hys, v core, v cl, v clrf, v pg#, v bootv, v ss, v gnd, v bg, v clset -0.3 v cca +0.3 v en v en 7v bst to pgnd static -0.3 36 v bst to pgnd transicent < 100ns 40 v bst to drn -0.3 7 v drn to pgnd static -2 30 v drn to pgnd transient < 100ns -5 34 v tg t stg -2 bst +0.3 v pgnd to agnd -0.3 0.3 v thermal resistance junction to ambient ja tssop-28 70 c/w thermal resistance junction to case jc tssop-28 20 c/w lead temperature (soldering) 10s t lead tssop-28 300 c peak ir re ow temperature 10 - 40s t pkg tssop-28 260 c parameter symbol conditions min typ max units supply (v in , v cca , v 5 ) v in supply voltage range v in 3.0 25 v v 5 supply voltage range v 5 4.3 5.0 6.0 v v cca voltage range v cca 4.5 5.0 6.0 v v cca quiescent current i ccq en is low 10 a en is high in uvlo 400 a absolute maximum ratings electrical characteristics
4 ? 2006 semtech corp. www.semtech.com power management SC453 parameter symbol conditions min typ max units v cca operating current i cc 5 ma under-voltage lockout circuits (v cca , v 5 ) threshold (v cca falling) v hcca 3.47 3.70 3.93 v v cca hysteresis v hyst cca 190 mv threshold (v 5 falling) v hv5 3.85 4.00 4.25 v v 5 hysteresis v hyst v5 210 mv fixed over-voltage protection (core) threshold (core rising) v th core fixed 1.95 2.00 2.05 v enable input (en) input high v ih (en) 2v input low v il (en) 0.8 v v core power good generator (pg_del, pg#) core input threshold v th core v dac = 0.6 - 1.75v note: during uvlo, the output level of this signal is unde ned upper threshold 1.1 v dac 1.15 v dac v lower threshold 0.86 v dac 0.9 v dac hysteresis 1 % pg# output voltage v pg# pulled up with external 680 resistor to v pull-up v core = v dac 0.4 v either v core < 0.88*v dac , or, v core > 1.12*v dac 0.95 v pull-up en is low or en is high but uvlo condition 0.95 v pull-up pg_del output voltage v pg_del v core = v dac pulled-up with external 680 resistor to v pull-up 1.2v 0.95 v pull-up v either v core < 0.88*v dac , or, v core > 1.12*v dac 0.4 en is low or en is high but uvlo condition 0.8 pg_del delay (at start-up) measured from pg# assertion 1007 clocks electrical characteristics (cont.)
5 ? 2006 semtech corp. www.semtech.com power management SC453 parameter symbol conditions min typ max units soft-start & dac slew (ss) soft-start/dac slew current note: ss cap is not discharged until en goes low or uvlo cuts in. to enable the converter, ss has to drop below v ss_en . i ss discharge (sink) current 5 10 ma soft-start transition 0 < t a < 85c, - 40 < t a < 85 c 7.5 10.5 16 a sleep exit, 0 < t a < 85c 204 256 310 sleep exit, -40 < t a < 85c 180 240 320 vid transition, 0 < t a < 85c 102 128 155 vid transition, -40 < t a < 85c 90 120 160 soft-start enable threshold v ss_en 40 100 mv dac (vid [5:0]) vid input threshold v ih_vid 0.55 v v il_vid 0.45 dac output voltage accuracy v dac_err 0 < t a < 85c, vid [5:0] = 000000 "11111 1(1.708v" 0.812v) -0.85 +0.85 % -25c < t a < 85c, vid [5:0] = 000000 "111111 (1.708v" 0.700v) -2.0 +2.0 % boot voltage (bootv) input voltage offset v bootv - v dac bootv = 1.2v |3| % boot delay time (1) tboot 10 35 s sleep (slp, slpv) input voltage offset v slpv -v dac slpv = 0.8v |3| % slp logic threshold v ih_slp 2 v v il_slp 0.8 core comparator (cmp, refin, hys) input bias current i refin v refin = 1.3v |2| a input voltage offset v cmp - v refin |1.5| |3| mv electrical characteristics (cont.)
6 ? 2006 semtech corp. www.semtech.com power management SC453 parameter symbol conditions min typ max units core comparator (cmp, refin, hys) (cont.) hysteresis setting current slp = low i cmp r hys = 17k v cmp < v refin -110 -100 -90 a v cmp > v refin 90 100 110 r hys = 170k v cmp < v refin -7 -10 -13 v cmp > v refin 71013 hysteresis setting current slp = high i slp_ i cmp r hys = 17k v cmp < v refin -83 -73 -63 a v cmp > v refin 63 73 83 current limit comparator (cl, clrf, hys) input bias current i cl v cl1, 2 = 1.3v |2| a input voltage offset v cl - v clrf |3| |5| mv current limit setting current slp = low i clrf r hys = 17k v cl < v clrf 150 200 250 a v cl > v clrf 250 300 350 r hys = 170k v cl < v clrf 15 20 25 v cl > v clrf 25 30 35 current limit setting current slp = high i slp_clrf r hys = 17k v cl < v clrf 120 150 180 a v cl > v clrf 195 230 265 zero-crossing (powersave) comparators (cl, core) offset v cl - v core |5| mv high side driver (tg) peak output current (1) i pkh 1.5 a output resistance r src_tg i = 100ma, v bst -v drn = 5v v drn < 1v 4.2 v drn > 1v 1 4 r sink_tg i = 100ma, v bst -v drn = 5v 0.7 1.4 rise time (1) tr tg c tg = 3nf, v bst -v drn = 5v 60 ns fall time (1) tf tg c tg = 3nf, v bst -v drn = 5v 36 ns electrical characteristics (cont.)
7 ? 2006 semtech corp. www.semtech.com power management SC453 parameter symbol conditions min typ max units high side driver (cont.) propagation delay tg going high (1) tpdh tg cmp crossing refin to 10% point of tg, c tg = 3nf, bg = 0v 45 ns propagation delay tg going low (1) tpdl tg cmp crossing refin to 90% point of tg, c tg = 3nf 45 ns shoot-thru protection delay time (1) tspd 21 30 39 ns low side driver (bg) peak output current (1) i pkl 3a output resistance r src_bg i = 100ma, v5 = 5v 1.0 2.6 r sink_bg 0.5 1.2 rise time (1) tr bg c bg = 3nf, v5 = 5v 25 ns fall time (1) tf bg c tg = 3nf, v = 5v 15 ns propagation delay tg going high (1) tpdh bg cmp crossing refin to 10% point of bg, c bg = 3nf, drn = 0v 35 ns propagation delay tg going low (1) tpdl bg cmp crossing refin to 90% point of tg, c tg = 3nf, drn = 0v 35 ns notes: 1) guaranteed by design. electrical characteristics (cont.)
8 ? 2006 semtech corp. www.semtech.com power management SC453 device package temp range(t j ) SC453tstrt tssop-28 -40c to + 125c SC453evb evaluation board notes: 1. only available in tape and reel packaging. a reel contains 2500 devices. 2. lead-free package compliant with j-std-020b. quali ed to support maximum ir re ow temperature of 260c for 30 seconds. 3. this device is esd sensitive. use of standard esd handling precautions is required. 4. all parameters subject to change without notice. 5. lead-free product. this product is fully weee and rohs compliant. pin# pin name pin function 1 drn this pin connects to the junction of the switching and synchronous mosfets. 2 tg output gate drive for the switching (high-side) mosfet. 3 bst bootstrap pin. a capacitor is connected between bst and drn pins to develop the oating bootstrap voltage for the high-side mosfet. 4 slp sleep logic input signal. 5 slpv connect this pin to v cca to select "vid sleep mode". otherwise, "slpv sleep mode" is selected and the voltage on this pin sets the dac output during sleep. 6 bootv the voltage on this pin sets the boot-up voltage. 7 pg# start clock indicator - open drain output. active low. 8 hys core comparator hysteresis. connect to ground thru an external resistor called r hys . hysteresis current is established by an internal v ref voltage, 1.7v, divided by r hys . 9 vid5 vid most signi cant bit main controller voltage programming dac input. 10 vid4 vid input. pin con guration ordering information pin descriptions 1 2 3 4 5 6 7 8 v5 drn top view (28 pin tssop) 27 28 15 16 bg tg pgnd bst en slp cl slpv cmp bootv clrf pg# vcca hys 9 10 22 refin vid5 gnd vid4 21 18 17 19 20 11 12 24 dac vid3 core vid2 23 25 26 13 14 pg_del vid1 ss vid0
9 ? 2006 semtech corp. www.semtech.com power management SC453 pin con guration pin descriptions (cont.) pin# pin name pin function 11 vid3 vid input. 12 vid2 vid input. 13 vid1 vid input. 14 vid0 vid least signi cant bit main controller voltage programming dac input. 15 ss soft-start. an external cap de nes the soft-start ramp. 16 pg_del delayed power good - open drain output. when the main converter output approaches and stays within 14% of the vid_dac setting, and the t cpu_pwrgd period has terminated. this signal is pulled high by an external resistor. 17 core main core converter output feedback to the power good generator. a small rc lter should be used to lter out any hf component to prevent faulty trip condition. 18 dac main controller digital-to-analog output. 19 gnd analog ground. 20 refin core comparator reference input pin. connect to dac. 21 vcca 5v supply for precision analog circuitry. 22 clrf current limit reference input pin 23 cmp core comparator input pin. 24 cl current limit input pin. 25 en enable - active high. this is capable of accepting a 5.0v signal level. 26 pgnd power ground. connect to the synchronous fet power ground. 27 bg output drive for the synchronous (low-side) fet. 28 v5 5vdc supply for the driver. a capacitor should be connected from v5 to gnd.
10 ? 2006 semtech corp. www.semtech.com power management SC453 block diagram ` ` vid/slpv sleep mode detect slpv bootv slp refin pg_del pg# ```
11 ? 2006 semtech corp. www.semtech.com power management SC453 applications information (cont.) supply, bias, uvlo, power good generator supply the chip is optimized to operate from a 5v 5% rail but also designed to work up to 6v maximum supply voltage. under-voltage lock-out circuit the under-voltage lock-out circuit consists of compara- tors which monitor the vcca and v5 voltage levels. the SC453 is in uvlo mode while either supply has not ramped above the upper threshold or has dropped below the lower threshold. during uvlo, the external fets are held off, tri-stating the output (drn). over-voltage protection if the core voltage is greater than +14% of the dac (i.e., out of the power good window), the SC453 will latch off and hold the low-side driver on permanently. either the power or en must be recycled to clear the latch. the latch is disabled during soft-start and vid/sleep transitions. for safety, the latch is enabled if the core voltage ex- ceeds 2v even during vid/sleep transitions. thermal shutdown the device will be disabled and latched off when the inter- nal junction temperature reaches approximately 160c. either the power or en must be recycled to clear the latch. band gap reference a 0.85% precision band gap reference acts as the in- ternal reference voltage standard of the chip, which all critical biasing voltages and currents are derived from. all references to vref in the equations to follow will assume vref = 1.7v. precision dac this 6-bit digital-to-analog converter (dac) serves as the programmable reference source of the core comparator. programming is accomplished by logic voltage levels ap- plied to the dac inputs. the vid code vs. the dac output is shown in the following table. the accuracy of the vid /dac is maintained on the same level as the band gap reference. vid v dac vid v dac 5432 10 v 5432 10 v 000000 1.708 100000 1.196 000001 1.692 100001 1.180 000010 1.676 100010 1.164 000011 1.660 100011 1.148 0 0 0 1 0 0 1.644 1 0 0 1 0 0 1.132 0 0 0 1 0 1 1.628 1 0 0 1 0 1 1.116 0 0 0 1 1 0 1.612 1 0 0 1 1 0 1.100 0 0 0 1 1 1 1.596 1 0 0 1 1 1 1.084 0 0 1 0 0 0 1.580 1 0 1 0 0 0 1.068 0 0 1 0 0 1 1.564 1 0 1 0 0 1 1.052 0 0 1 0 1 0 1.548 1 0 1 0 1 0 1.036 0 0 1 0 1 1 1.532 1 0 1 0 1 1 1.020 0 0 1 1 0 0 1.516 1 0 1 1 0 0 1.004 0 0 1 1 0 1 1.500 1 0 1 1 0 1 0.988 001110 1.484 101110 0.972 001111 1.468 101111 0.956 010000 1.452 110000 0.940 0 1 0 0 0 1 1.436 1 1 0 0 0 1 0.924 0 1 0 0 1 0 1.420 1 1 0 0 1 0 0.908 0 1 0 0 1 1 1.404 1 1 0 0 1 1 0.892 0 1 0 1 0 0 1.388 1 1 0 1 0 0 0.876 0 1 0 1 0 1 1.372 1 1 0 1 0 1 0.860 0 1 0 1 1 0 1.356 1 1 0 1 1 0 0.844 0 1 0 1 1 1 1.340 1 1 0 1 1 1 0.828 0 1 1 0 0 0 1.324 1 1 1 0 0 0 0.812 0 1 1 0 0 1 1.308 1 1 1 0 0 1 0.796 0 1 1 0 1 0 1.292 1 1 1 0 1 0 0.780 0 1 1 0 1 1 1.276 1 1 1 0 1 1 0.764 0 1 1 1 0 0 1.260 1 1 1 1 0 0 0.748 0 1 1 1 0 1 1.244 1 1 1 1 0 1 0.732 011110 1.228 111110 0.716 011111 1.212 111111 0.700
12 ? 2006 semtech corp. www.semtech.com power management SC453 dac slew control the output of the dac will slew at a rate de ned by the current in the ss pin and the capacitor applied externally to the ss pin. the slew rate (charge current) applied de- pends on which mode (soft-start, vid or sleep transition) is in effect. the ss capacitor together with the dac ca- pacitor will determine the stability of the dac, a 1nf ca- pacitor is recommended for the dac pin. blanking during vid changes on any vid change or sleep change, the pg# and pg_ del signals are blanked for 62 switching cycles to prevent glitching during the transition. sleep function in sleep mode, the dac output is set by the voltage on the slpv pin when the slp pin is held high. in "vid sleep" mode, the dac output is set by the vid bits when slp is held high. during sleep, the hysteresis and current limit hysteresis currents are reduced to 70% of their nominal values. slpv/vid sleep mode by default, the controller is in "slpv controlled sleep" mode. in this mode, the voltage applied to the slpv pin appears at the dac output when slp is asserted. by holding the slpv pin at vcca during start-up, "vid con- trolled sleep" mode is engaged. in this mode, the dac out- put continues to be set by the vid inputs even when slp is asserted. core converter controller core comparator this is an ultra-fast hysteretic comparator with a typical propagation delay of about 20ns at a 20mv overdrive. hysteresis is generated by the current set at the hys pin impressed upon an external resistor connected to the cmp pin. current limit comparator the current limit comparator monitors the core converter output current and turns off the high side fets when the current exceeds the upper current limit threshold, vhcl and is re-enabled only if the phase current drops below the lower current limit threshold, vlcl. the current is sensed by monitoring the voltage drop across the current sense resistor, rcs connected in series with the core con- verter inductor. vhcl and vlcl are xed by the current set at the hys pin impressed upon an external resistor connected to the clrf pin. current limit latch if the core voltage goes lower than 14% below the vid (i.e., out of the power good window), then sustained cur- rent limiting (32 current limit pulses) will cause the part to permanently latch off. the latch is inhibited during soft- start. core converter soft-start timer this block controls the start-up ramp time of the core voltage up to the boot voltage. the primary purpose is to reduce the initial in-rush current on the core input voltage (battery) rail. cycle-by-cycle power-save a zero crossing comparator detects when the currents through the external sense resistor reduces to zero. when the current in the external sense resistor reaches zero, the bottom fet is latched off. the latch is reset when the controller decides to switch on the top fet. this prevents excessive switching at light loads and hence saves switch- ing power losses. applications information (cont.)
13 ? 2006 semtech corp. www.semtech.com power management SC453 applications information (cont.) pg# output this is an open-drain output and should be pulled up ex- ternally. this signal is asserted (pulled low) by the SC453 whenever the core voltage is within 14% of the vid programmed value. if the chip is disabled or enabled in uvlo, then pg# is de-asserted. during start-up pg# re- mains de-asserted until the core voltage has reached the de ned boot voltage and remains there for the boot pe- riod (10 s minimum). this signal is forced low (asserted) during vid and sleep transitions. pg_del output this signal is delayed a minimum of 3ms from rst as- sertion of the pg# signal. this is an open drain output and should be pulled up externally. this signal is asserted (open drain) by the SC453 whenever the core is within 14% of the vid programmed value. if the chip is disabled or enabled in uvlo, then pg_del is de-asserted. the sig- nal is forced high (open drain) during vid and sleep transi- tions. start-up and sequencing on start-up, v core ramps to the boot voltage set by the bootv pin irrespective of the status of the vid pins. after a minimum of 10 s, pg# asserts, and v core responds to the vid inputs. the controller will then count 1007 switch- ing cycles before asserting pg_del. summary of fault conditions driver timing diagram cmp bg tg cmprf tf tpdl tpdh tr tpdl tf ts pd tr tg tg tg bg bg bg bg tpdh tg (4) (4) note (4): subtract a typical value of 17ns for the core comparator delay since this parameter is speci ed from a cmp edge. protection mode latched? when active driver status ss pin status supply uvlo (vcca, v5) no always all low low 32 cycle current limit yes ss has terminated and pgdel is low tg low sawtooth 114% v core ovp yes ss has terminated and pgdel is low bg high high 2.0v core ovp yes always bg high high thermal shutdown yes always bg, tg low high refin
14 ? 2006 semtech corp. www.semtech.com power management SC453 applications information (cont.) design procedure step 1: de ne constants maximum input voltage minimum input voltage maximum load current, highest output voltage leakage current, highest output voltage the highest v core voltage the lowest v core voltage SC453 internal reference voltage output capacitance per cap esr per cap current sense resistor parasitic resistance from the current sense resistor to the processor voltage droop allowed for a low current to high current transient voltage rise allowed for a high current to low current transient desired maximum output ripple step 2: output inductor and capacitor selection the SC453 has "passive" droop. the voltage at full load is less than the dac voltage by the voltage drop across the current sense resistor and any pcb copper losses from the sense resistor to the processor socket. the steady- state voltage at full load is: v max_fl v max_nl r cs r cu + () i max_fl ? ? := v max_fl 1.182 v = output capacitance and esr values are a function of transient requirements and output inductor value. figure 1 illustrates the response of a hysteretic converter to a positive transient. in a hysteretic converter with passive droop, like the SC453, two conditions determine if you meet the positive transient requirements. a. esr v pos_trans i max_fl i lkgmax ? ( ) b. v neg_trans deltav c out () figure 1 - hysteretic converter response to a positive transient the rst condition is easy to see; if the esr is too high, the transient response will fail. v inmax 20v := v inmin 8v := i max_fl 20a := i lkgmax 5a := v max_nl 1.212v := v min_nl 0.956 v ? := v ref 1.7v := c out 330 f ? r esr 6m ? := r cs 1m ? := r cu 0.5m ? := v pos_trans 50m v := v neg_trans 50mv := v ripple 20m v :=
15 ? 2006 semtech corp. www.semtech.com power management SC453 in the second condition, because the hysteretic converter responds in < 100ns, the capacitor does not droop very far before the inductor current starts ramping up. (this is not true of control schemes where time constants in the error ampli er cause delays.) once the inductor current starts to rise, the increasing ? v of the capacitor is offset by reduced ? v from the esr, so ? v is constant. if the ? v due to the charge taken from the capacitor before the in- ductor current reaches the load current (note the shaded area on the graph) is less than vpos_trans, then the transient response passes. since the highest output voltage has the most severe re- quirements, any other modes are satis ed by a design op- timized for the highest output voltage. c. for the second condition, we need to know the inductor value, which is a function of the highest desired switching frequency. the maximum frequency occurs at the high- est input voltage. as a reasonable compromise between ef ciency and component size, a maximum switching fre- quency of 350khz is desired. d. e. f. based on the following four factors: 1) minimum induc- tance requirement; 2) device availability at the time we designed the evaluation board; 3) low dcr ; 4) height and package size consideration. keep in mind, the choice you make should be based upon the requirement of the con- verter design, including minimum inductance, minimum saturation current, ef ciency, foot area, maximum allow- able height, and of course, device availability. in the cur- rent demo board design, g. this value of inductance is required up to maximum load. inductors with a ?swinging choke? characteristic, where the zero current value of inductance is much less than the full load current inductance can be used, as long as the above restriction is met. then, the worst-case (low input voltage) response time (the time for the current to reach the new transient value) is: h. add ~100ns for the propagation delay from a change at the output to the mosfet switch turning on in reaction. since the shaded area is triangular, the total charge taken out of the capacitor = (di / dt) / 2. q = c / dv = (di / dt) / 2, therefore; i. c minp i max_fl i lkgmax ? () dt 1 10 7 ? ? sec ? + ( ) ? v pos_trans := c minp 4.278 10 4 ? f = this condition applies only to the positive transient. l min d min v inmax v max_nl ? () esr max r cs + () ? f s v ripple ? esr max r cs + esr max ? ? ? ? ? ? ? := l min 5.422 10 7 ? h = d min v max_nl v inmax := applications information (cont.) esr max v pos_trans i max_fl i lkgmax ? ( ) := esr max 3.333 10 3 ? = l 1 0.60 h ? := f s 350k h z ? := dt l 1 i max_fl i lkgmax ? () ? v inmin v max_nl ? := dt 1.326 10 6 ? s =
16 ? 2006 semtech corp. www.semtech.com power management SC453 load release the worst-case for the transient load release to happen is when the hysteresis has just reached the maximum, (i.e., the high-side switch has just turned of); at this time the inductor has reached its peak current. i ripple v inmax v max_fl ? () d min ? l 1 f s ? l 1 l min ? := i t0 i max_fl i ripple 2 + := load is stepping from high to low. immediately after the load steps down from i max to i min , the high side fet is turned off, and the bottom fet is turned on after the dead time. we assume for the worst-case condition, at t = 0, the output inductor is sitting at its max- imum; after t = 0, the inductor discharges at a rate equal to v fl / l. (without the consideration of the secondary or- der effect, such as, rds_on drop, current sense resistor and copper losses). the energy released from the output inductor during load step-down, charges the output ca- pacitors and is dissipated through the following means: rds_on, rcs, rcu, rcu_rt, esr of the output capacitors and load. applications information (cont.) since the output inductor is discharging at a xed rate, there are two terms contributing to the increase of the voltage on the output capacitors: 1) is due to the esr of the output capacitor; 2) is due to the added charge con- tributed by the inductor current. j. v esr tn cap , () i cap t () r esr n cap ? := k. dv cap tn cap , () i cap t ()t ? c out n cap ? := l. v total tn cap , () v esr tn cap , () dv cap tn cap , () + := the chart above shows the system response for the ca- pacitors de ned in step 1 and the chart to follow shows the details of the response for the chosen number of out- put capactors. lr ds r cu esr_eq i max i min cout_eq rcu_rt rds_on bg r_load t010ns ? , 10 s ? .. := i l t () i t0 v max_fl t ? l 1 ? ? ? ? ? ? := i cap t () i l t () i lkgmax ? := i ripple 6.01 a = i t0 23.005 a =
17 ? 2006 semtech corp. www.semtech.com power management SC453 applications information (cont.) step 3: setting rhys the next step is to calculate r hys . since the SC453 is a hysteretic controller, it regulates the amount of output ripple according to a hysteresis value set by r hys . the de- signer must therefore decide upon the amount of desired output ripple, and then set r hys accordingly. the hysteresis controls the amount of ripple at the point of regulation, which is the point between the inductor and the current sense resistor. the amount of ripple at the output is de ned by the current sense resistor and the output cap, esr. this factor is taken into account in the equation shown below relating v ripple to v hys . to achieve tight accuracy, it is recommended that the out- put ripple be set to 20mv peak-to-peak. esr r esr n cap := esr 1.5 10 3 ? = v ripple 0.02 v = m. v hys v ripple r cs esr + () esr ? := v hys 0.033 v = v hys is created by a current source, i hys , through r9 (see the diagram below). the current source value is con- trolled via r hys . for simplicity it is easier to select a value for r7 (the resistor in series with the cmp pin) rst, and then calculate r hys , as follows: n. r 7 1k ? := . r hys 2v ref ? v hys r 7 ? ? ? ? ? := r hys 102.0 k = in the SC453 application circuit, r hys consists of three re- sistors (r3, r4 and r5). these resistors also form the dividers for bootv and slpv. note also that depending on circuit layout and parasitics, r hys may have to be ad- justed slightly to obtain optimum performance. (we will come back to calculate the above resistors after we set the pboot and deeper sleep voltages). to increase hys- teresis without having to change the divider resistors, a fourth resistor (r14), can be added. additional hysteresis is needed when inductances in the current sense paths cause additional signal that add to the resistive signal, limiting the accuracy of the calculations. r14 hys bootv slpv r5 r4 r3 SC453
18 ? 2006 semtech corp. www.semtech.com power management SC453 step 4: bootv design the boot-up voltage for v core is set at 1.2v. for the SC453 typical application circuit, r3, r4, and r5 form a voltage divider off v ref and are used to set the boot voltage. for simplicity, we de ne r boot : = r3 + r4. v boot 1.2v := o. r hys 1 1 r 25 1 r boot r 5 + + := p. r boot v boot r 5 ? v ref v boot ? := step 5: sleep voltage design the sleep voltage is set at 0.750v nominally using the r3 - r4 - r5 divider. q. v slp 0.750 v := r3, r4 and r5 are calculated using a matrix to solve the simultaneous equations. r14 is set at 1m as a place- holder: r 14 1000 k := m x 1 1 1 1 1 v slp 1 ? v ref v slp ? ? 1 v boot v ref v boot ? ? v slp 1 ? v ref v slp ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? := applications information (cont.) from the standard 1% resistor value table, we choose the following values according to the calculation results: r5 = 33.2k . r4 = 30.1k r3 = 49.9k step 6: current limit calculation setting the threshold for current limit is a relatively straightforward process. to do this we must calculate the peak current based on the maximum dc value plus the worst-case ripple current. the following calculations apply for a single phase. worst-case ripple occurs at the high- est input voltage. since ripple is also inversely proportion- al to inductance, it is recommended that the minimum inductance value be used based on the manufacturer?s speci ed tolerance: l low l 1 120% ? () ? := l low 4.8 10 7 ? h = r. i ripple_max v inmax v max_nl ? () d min ? l low f s ? := v r 14 r hys ? r 14 r hys ? 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? := soln lsolve m x v , () := soln 5.011 10 4 3.007 10 4 3.341 10 4 ? ? ? ? ? ? ? ? ? ? ? = r 4 3.007 10 4 = r 4 010 ( ) soln ? := r 5 3.341 10 4 = r 5 001 ( ) soln ? := r 3 100 ( ) soln ? := r 3 5.011 10 4 = r 3 v slp r 4 r 5 + () v ref v slp ? ? := i ripple_max 6.777 a =
19 ? 2006 semtech corp. www.semtech.com power management SC453 applications information (cont.) to calculate the maximum dc value of current we must add the maximum dc current and the maximum ripple value to obtain peak current: s. it is recommended that the current limit be set at 120% of the peak value to allow for inductor current overshoot during load transients: t. the current limit comparator internal to the SC453 moni- tors the output current and turns the high side switch off when the current exceeds the upper current limit thresh- old, i clmax and re-enables only if the load current drops be- low the lower current limit threshold, i clmin . the current is sensed by monitoring the voltage drop across the current sense resistor r cs . current limiting will cycle from i clmax to i clmin for 32 switch- ing cycles to allow for short term transients, then the con- verter is latched off. i clmax and i clmin are set according to the following equations: u. we set the current limit at i clim = iclmax, and then solve for r cl , which is r6 in the typical applications circuit. for balance, r8, in series with the clrf pin is kept the same value as r6. v. r cl i clim r hys ? r cs ? 2.5 v ref ? := r cl 673.59 = r 6 681 := r 8 r 6 := r 8 681 = step 7: small capacitors/resistor selection several small capacitors are required for signal ltering. use smt ceramic capacitors with an x7r or better tem- perature coef cient. cog is preferred. c11, which lters the output voltage feedback, is sized to provide ltering beyond the 5th harmonic of the funda- mental. c11 1 2 ? r 7 ? f s ? 5 ? := w. c11 9.095 10 11 ? f = in the evaluation board design, we use 100pf, 603, x7r ceramic caps for c11. the dac output requires a 1nf, x7r or cog capacitor (c23) for high frequency noise l- tering. the values for c12 and c13 are calculated in a similar manner, though they are returned to the core pin because that is the reference point for the current limit comparator. x. c 12 1 2 ? r 6 ? f s ? 5 ? := c 13 c 1 2 := c 12 1.335 10 10 ? f = c 13 1.335 10 10 ? f = i peak 23.389 a = i peak i max_fl i ripple_max 2 + := i clim 120% i pea k ? := i clim 28.066 a = i clmax 3v ref ? r cl r hys r cs ? ? := i clmin 2v ref ? r cl r hys r cs ? ? :=
20 ? 2006 semtech corp. www.semtech.com power management SC453 based on the above calculations, we choose n = 4 for the input capacitor. step 9: ovp no calculations are necessary for over-voltage protection. if v core is greater than +14% of the dac (i.e., out of the power good window), the SC453 will latch off and hold the low-side driver on permanently (for each phase). either the power or en must be recycled to clear the latch. the latch is disabled during soft-start and vid/deepersleep transitions. the latch is enabled if v core exceeds 2v even during vid/deepersleep transitions to ensure that the processor maximum is not exceeded. the table on page 13 is a summary of fault conditions using SC453. step 10: soft-start/dac slew control the soft-start cap c21 in the SC453 design serves three conditions: 1) to de ne the soft-start ramp; 2) to de ne the dac slew rate during sleep and vid transitions (dur- ing vid transitions the ss current is nominally +/- 120 a. during sleep transitions the ss current increases to +/- 240 a); 3) during start-up, the ss current is normally +/- 6.5 a. we will be doing three soft-start exercises based on the above three conditions for SC453 application: step 8: calculate input rms current in order to calculate the worst-case input rms current, we need to assume the ef ciency at v in_min and full load. from the measurement result, we are safe to assume 80%, (this number is very conservative, actual ef ciency should be much higher). the actual converter ef ciency depends on component selection, layout, air ow, etc. p out i max_fl v max_f l ? := p out 23.64 w = p in p out 85% := i in_dc p in v inmin := d v max_fl v inmin := i in_dc 3.476 a = i rms i max_fl () i in_dc ? ? ? ? 2 d ? i in_dc 2 1d ? () ? ? ? ? + := i rms 7.116 a = c i_rms 2a := 10 f@25v, mlcc cap from panasonic is rated 2a rms. c i_num ceil i rms c i_rms ? ? ? ? ? := c i_num 4 = the calculation indicates four of these mlcc caps satisfy the worst-case rms current requirement. input capacitance calculation: (based on ripple voltage) dvin is the allowable input ripple voltage contributed by the amount of input capacitance. for this exercise, we use 250mv as the allowable input ripple voltage. the maximum value occurs at d = 0.5 applications information (cont.) dvin 250m v := d max 0.5 := t in 1 f s := c in_min i peak 2 d max d max 2 ? ? ? ? ? t in dvin ? := c in_min 3.341 10 5 ? f = c in 10 f n in_min_ripple ceil c in_min c in ? ? ? ? ? := n in_min_ripple 4 =
21 ? 2006 semtech corp. www.semtech.com power management SC453 applications information (cont.) 1. start-up: i ss 6.5 a := dt su 3ms := dv dacsu v max_n l := c ss_max_startup i ss dt su ? dv dacsu := c ss_max_startup 1.609 10 8 ? f = 2. vid change: i ssv 120 a := dt v 100 s := dv dacv v max_nl v min_n l ? := c ss_max_vid i ssv dt v ? dv dacv := c ss_max_vid 4.687 10 8 ? f = 3. sleep entry/exit: i sss 240 a := dt s 33 s dv dacs v max_nl v slp ? := c ss_max_drs i sss dt s ? dv dacs := c ss_max_drs 1.714 10 8 ? f = exercise #1 predicts the max capacitance allowed. in order to allow tolerance, we choose c22 = 15nf.
22 ? 2006 semtech corp. www.semtech.com power management SC453 n a a2 a1 bxn e1 .378 9.60 .386 9.70 9.80 plane bbb c a-b d ccc c dimensions "e1" and "d" do not include mold flash, protrusions 3. or gate burrs. datums and to be determined at datum plane controlling dimensions are in millimeters (angles in degrees). -b- notes: 1. 2. -a- -h- side view a b c d e h e/2 (.039) .008 - .004 .024 - - - - 0 l (l1) c 01 gage plane see detail detail a a 0.25 .026 bsc .252 bsc 28 .004 .169 .173 .007 - 28 0.10 0.65 bsc 6.40 bsc 4.40 - .177 4.30 .012 0.19 4.50 0.30 .382 2x n/2 tips seating aaa c e/2 indicator pin 1 2x 2 13 .018 .003 .031 .002 - 8 0 0.20 0.10 - 8 0.45 0.09 0.80 0.05 .030 .007 .047 .042 .006 - 0.60 (1.0) - 0.75 0.20 - - - 1.20 1.05 0.15 d reference jedec std mo-153, variation ae. 4. inches b n bbb aaa ccc 01 e1 e l l1 e d c dim a1 a2 a min max millimeters dimensions min max nom nom e marking information outline drawing - tssop-28
23 ? 2006 semtech corp. www.semtech.com power management SC453 land pattern - tssop-28 (.222) (5.65) z g y p (c) 4.10 .161 0.65 .026 0.40 .016 1.55 .061 7.20 .283 x inches dimensions z p y x dim c g millimeters this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1. semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 contact information www.semtech.com

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